The present invention relates, in general, to the field of integrated circuit memories (“DRAMs”). More particularly, the present invention relates to a method of refreshing the row decoders in an integrated circuit that conserves power from an on-chip pumped high voltage source.
A highly simplified block diagram of a typical DRAM 10 is shown in FIG. 1. A single memory bank 14 includes a plurality of individual memory subarrays 16. Row decoders 12 and other row path circuits such as precharging circuits are coupled to the word lines of the memory cells found in subarrays 16. Column decoder 18 is coupled to the bit lines of the memory cells found in subarrays 16. Row decoder block 12 receives, among many other signals not shown, a PRE precharge command signal, a clock signal, and an array select signal.
In a typical DRAM 10 a high voltage precharge clock is used to precharge the row decoders and other row path circuits. These row path circuits drain current from a high voltage pumped supply (“VCCP”). This current can be significant, and since the high voltage supply is provided by an on-chip voltage pump, the current required from the external low voltage supply is a multiple of the internal high voltage current due to the efficiency of the voltage pump, which is typically in the range of 25% to 33%.
When a precharge command is initiated, the address of the bank to be precharged is used to activate only the internal high voltage precharge clocks that are needed to precharge the row circuitry in all of the sub-arrays in this one bank. Typically, a single memory bank 14 may contain 2–16 or more subarrays. The bank precharge function reduces the current from the high voltage supply compared to precharging all banks simultaneously.
An example of a prior art precharged row decoder 20 is shown in FIG. 2. Notice that all of the gates and transistors in row decoder 20 are directly or indirectly coupled to the pumped VCCP high voltage power supply. An input section includes a P-channel transistor M1 for receiving the precharge clock signal P0B, an N-channel transistor M2 coupled to VCC, an N-channel transistor M3 for receiving an “R543” control signal, and an N-channel transistor M4 for receiving the array select signal (“ASEL”). The input section is coupled to a latch including cross-coupled inverters INV1 and INV2. The latch is in turn coupled to the WL word line output through serially coupled inverter INV3 and a level shifting inverter.
As can be seen in the timing waveforms shown in FIG. 3, signal P0B goes low to precharge (reset) the row decoder 20. Assume, for example, that there are 33 row decoders for each subarray and eight subarrays in each bank. Therefore, where a bank precharge command is given to the DRAM macro, the P0B precharge clock signal for an entire bank (8×33=264 row decoders) must switch to a low state and then back to a high state (VCCP power supply level). Since the P0B signal is connected to 264 PMOS transistors (transistor M1 in row decoder 20), there is a large capacitance on the P0B signal line, which results in a large amount of current flowing from the VCCP high voltage supply when P0B transitions to a high state.
A prior art P0B precharge clock generator 40 is shown in FIG. 4. An input NAND gate receives the PRE precharge control signal. A transmission gate circuit including P-channel transistor M3 and N-channel transistor M4 is coupled to the output of the input NAND gate. An N-channel transistor M5 is coupled between the inverting switching input of the transmission gate and the output of the transmission gate. An inverter INV6 is coupled between the non-inverting and inverting switching inputs of the transmission gate. A delay circuit including serially-coupled inverters is coupled between the CLK input and the second input to the NAND gate. An output level shifter receives power from the VCCP power supply and provides the output P0B precharge clock signal.
With reference to the timing diagram of FIG. 5, if the precharge signal PRE is high when the clock signal CLK goes high, then the output precharge clock signal P0B goes low. The PRE precharge signal is an internal bank precharge command signal. There is one PRE signal for each bank. Therefore, for example, if there are four total memory banks for a particular design, then four PRE signals are required. After CLK goes high, node N4 goes high after a delay through serially coupled inverters INV7, INV8, INV9, and NAND1. This causes node N6 to go low and output P0B to go high. As stated earlier, the P0B precharge clock signal is connected to all of the row decoders in a bank in prior art memory architecture 10.
What is desired, therefore, is a circuit and method of operation that retains the benefits of the previously described circuit, but would precharge only the row circuits in the subarrays that have been previously activated instead of all the subarrays within a bank. This reduces the current from the internal high supply by the ratio of the number of subarrays in one bank. In order to limit integrated circuit size and cost, the reduction in precharge current is ideally accomplished without using extra address inputs to determine which subarrays to precharge.